CY28401
function may be implemented in two ways, via writing a ‘0’ to
SMBus register bit or by asserting the SRC_DIV2# input pin
LOW. In both methods, if the SMBus register bit has been
written LOW or the SRC_DIV2# pin is LOW or both, all DIF
outputs will configured for divide by 2 operation.
OE Assertion (Transition from ‘0’ to ‘1’)
All differential outputs that were three-stated will resume
normal operation in a glitch-free manner. The maximum
latency from the assertion to active outputs is between 2–6 DIF
clock periods. In addition, DIFT clocks will be driven HIGH
within 10 ns of OE assertion to a voltage greater than 200 mV.
SRC_DIV2# Assertion
The impact of asserting the SRC_DIV2# is that all DIF outputs
will transition cleanly in a glitch-free manner from normal
operation (output frequency equal to input) to half the input
frequency within 2–6 DIF clock periods.
OE Deassertion (Transition from ‘1’ to ‘0’)
The impact of deasserting OE is each corresponding output
will transition from normal operation to three-state in a
glitch-free manner. The maximum latency from the
deassertion to three-stated outputs is between 2–6 DIF clock
periods.
SRC_DIV2# Deassertion
The impact of deasserting the SRC_DIV2# is that all DIF
outputs will transition cleanly in a glitch-free manner from
divide by 2 mode to normal (output frequency is equal to the
input frequency) operation within 2–6 DIF clock periods.
LOCK Signal Clarification
The LOCK output signal is intended to provide designers a
signal indicating that PLL lock has been achieved and valid
clock are available. This can be helpful when cascading
multiple buffers that each contribute a 1-ms start-up delay in
addition to the start-up time of the clock source. Upon
receiving a valid clock on the SRC_IN input (PWRDWN#
deasserted), the buffer will begin ramping the internal PLL until
lock is achieved and stable, the clock buffer will assert the
LOCK pin HIGH and enable DIF output clocks. In other words,
if power is valid and PWRDWN# is deasserted but no input
clocks are present on the SRC_IN input, all DIF clocks remain
disabled. Only after valid input clocks are detected, valid
power, PWRDWN# deasserted with the PLL locked and stable
are LOCK to be asserted and the DIF outputs enabled. The
maximum start-up latency from valid clocks on SRC_IN input
to the assertion of LOCK (output clocks are valid) is to be less
than 1 ms. Once LOCK has been asserted high, it will remain
high (regardless of the actual PLL status) until power is
removed or the PWRDWN# pin has been asserted.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass
mode (no PLL) and PLL mode. In bypass mode, the input clock
is passed directly to the output stage resulting in 50-ps additive
jitter (50 ps + input jitter) on DIF outputs. In the case of PLL
mode, the input clock is pass through a PLL to reduce
high-frequency jitter. The BYPASS# mode may be selected in
two ways, via writing a ‘0’ to SMBus register bit or by asserting
the PLL/BYPASS# pin LOW. In both methods, if the SMBus
register bit has been written LOW or PLL/BYPASS# pin is
LOW or both, the device will be configured for BYPASS
operation.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This
mode is intended to minimize PLL peaking when two or more
buffers are cascaded by staggering device bandwidths. The
PLL low-bandwidth mode may be selected in two ways, via
writing a ‘0’ to SMBus register bit or by asserting the
HIGH_BW# pin is LOW or both; the device will be configured
for low-bandwidth operation.
SRC_DIV2# Clarification
The SRC_DIV2# input is used to configure the DIF output
mode to be equal to the SRC_IN input frequency or half the
input frequency in a glitch-free manner. The SRC_DIV2#
Rev 1.0,November 21, 2006
Page 9 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
