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CY28400OXC-2 参数 Datasheet PDF下载

CY28400OXC-2图片预览
型号: CY28400OXC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz差分缓冲器,用于PCI Express和SATA [100 MHz Differential Buffer for PCI Express and SATA]
分类和应用: PC
文件页数/大小: 15 页 / 238 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28400OXC-2的Datasheet PDF文件第7页浏览型号CY28400OXC-2的Datasheet PDF文件第8页浏览型号CY28400OXC-2的Datasheet PDF文件第9页浏览型号CY28400OXC-2的Datasheet PDF文件第10页浏览型号CY28400OXC-2的Datasheet PDF文件第11页浏览型号CY28400OXC-2的Datasheet PDF文件第13页浏览型号CY28400OXC-2的Datasheet PDF文件第14页浏览型号CY28400OXC-2的Datasheet PDF文件第15页  
CY28400-2  
AC Electrical Specifications (continued) (Measured in High Bandwidth Mode)  
Parameter  
'VOX  
Description  
Vcross Variation over all edges  
Differential Ringback Voltage  
Time before ringback allowed  
Absolute maximum input voltage  
Absolute minimum input voltage  
DIFT and DIFC Duty Cycle  
Rise/Fall Matching  
Condition  
Min.  
Max.  
140  
Unit  
mV  
mV  
ps  
V
Measured SE  
VRB  
–100  
500  
100  
TSTABLE  
VMAX  
1.15  
VMIN  
–0.3  
45  
V
TDC  
Measured at crossing point VOX  
55  
20  
%
TRFM  
Determined as a fraction of 2*(TR – TF)/(TR + TF)  
%
DIF at 0.7V  
FIN  
Input Frequency  
Bypass or PLL 1:1  
90  
210  
0
MHz  
ppm  
%
FERROR  
TDC  
Input/Output Frequency Error  
DIFT and DIFC Duty Cycle  
Average Period  
Bypass or PLL 1:1  
Measured at crossing point VOX  
Measured at crossing point VOX at 100 MHz  
45  
55  
TPERIOD  
TR / TF  
9.9970 10.0533 ns  
DIFT and DIFC Rise and Fall Times  
Single ended measurement: VOL = 0.175 to  
VOH = 0.525V (Averaged)  
175  
700  
ps  
TRFM  
Rise/Fall Matching  
Determined as a fraction of  
2 * (TR – TF)/(TR + TF)  
20  
%
'TR/'TF  
Rise and Fall Time Variation Variation Single ended measurement: VOL = 0.175 to  
VOH = 0.525V (Real Time)  
125  
ps  
VHIGH  
VLOW  
VOX  
Voltage High  
Voltage Low  
Measured SE  
Measured SE  
660  
–150  
250  
850  
mv  
mv  
mv  
mV  
V
Crossing Point Voltage at 0.7V Swing Measured SE  
550  
140  
'VOX  
VOVS  
Vcross Variation over all edges  
Maximum Overshoot Voltage  
Measured SE  
Measured SE  
VHIGH  
0.3  
+
VUDS  
VRB  
Minimum Undershoot Voltage  
Ring Back Voltage  
Measured SE  
0.2  
–0.3  
N/A  
50  
V
Measured SE  
V
TCCJ  
Cycle to Cycle Jitter  
PLL Mode  
ps  
ps  
ps  
ps  
ns  
Bypass Mode (Jitter is additive)  
Measured at crossing point VOX  
Measured at crossing point VOX  
50  
TSKEW  
TPD  
Any DIFT/C to DIFT/C Clock Skew  
Input to output skew in PLL mode  
50  
250  
4.5  
Input to output skew in Non-PLL mode Measured at crossing point VOX  
2.5  
M e a s u re m e n t  
P o in t  
T P C B  
4 9 .9 :  
3 3 :  
3 3 :  
D IF T  
2 p F  
M e a s u re m e n t  
P o in t  
T P C B  
4 9 .9 :  
D IF C  
IR E F  
2 p F  
4 7 5 :  
T ra c e Im p e d a n c e M e a s u re d D iffe re n tia lly  
Figure 12. Differential Clock Termination  
Rev 1.0,November 21, 2006  
Page 12 of 15  
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