CY28358
200-MHz Differential Clock Buffer/Driver
Description
Features
• Up to 200 MHz operation
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential output levels.
• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize the
outputs to the clock input
• Conforms to the DDR1 specification
• Spread Aware™ for EMI reduction
• 28-pin SSOP package
The two line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
Block Diagram
Pin Configuration
10
CLKC0
CLKT0
VDD
GND
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKT0
CLKC0
CLKC5
CLKT5
CLKC4
CLKT4
VDD
2
3
CLKT1
CLKC1
CLKT1
CLKC1
GND
4
5
CLKT2
CLKC2
Serial
Interface
Logic
SCLK
6
SDATA
NC
SCLK
CLKIN
NC
7
SDATA
CLKT3
CLKC3
8
FBIN
9
FBOUT
NC
AVDD
CLKT4
CLKC4
10
11
12
13
14
CLKIN
FBIN
AGND
VDD
PLL
CLKT3
CLKC3
GND
CLKT5
CLKC5
CLKT2
CLKC2
FBOUT
AVDD
28 pin SSOP
Rev 1.0, November 20, 2006
Page 1 of 10
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2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
SPECTRALINEAR [ SPECTRALINEAR INC ]
