CY28349
Data Byte 16
Power On
Default
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
--
Name
Pin Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
Data Byte 17
Power On
Default
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
--
Name
Pin Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
Table 4. Frequency Selection Table
Input Conditions
Output Frequency
PLL Gear
Constants
(G)
FS4
FS3
FS2
FS1
FS0
SEL4
SEL3
SEL2
SEL1
SEL0
CPU
3V66
67.1
67.3
72.0
67.5
76.0
78.0
80.0
82.0
63.0
65.0
67.0
67.1
67.3
74.0
76.0
78.0
80.0
82.0
PCI
33.6
33.6
36.0
33.7
38.0
39.0
40.0
41.0
31.5
32.5
33.5
33.6
33.6
37.0
38.0
39.0
40.0
41.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.7
100.9
108.0
101.2
114.0
117.0
120.0
123.0
126.0
130.0
133.9
134.2
134.5
148.0
152.0
156.0
160.0
164.0
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Rev 1.0,November 24, 2006
Page 12 of 20