CY28346
AC Parameters (VDD = VDDA = 3.3V 5%, TA = 0°C to +70°C) (continued)
66 MHz 100 MHz
133 MHz
200 MHz
Parameter
Description
Min.
1.0
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit Notes
TPZL/TPZH
Output Enable Delay
(All Outputs)
10.0
1.0
10.0
1.0
10.0
1.0
10.0
10.0
3
ns
10
10
10
T
PZL/TPZH
Outputdisabledelay(all 1.0
outputs)
10.0
3
1.0
10.0
3
1.0
10.0
3
1.0
ns
TSTABLE
All Clock Stabilization
from Power-up
ms
TSS
TSH
TSU
Stopclock Set-up Time
Stopclock Hold Time
Oscillator Start-up Time
10.0
0
10.0
0
10.0
0
10.0
0
ns
ns
27
27
28
X
X
X
X
ms
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Figure 16. VTT_PWRGD# Timing Diagram29[29]
Off
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 (0,1)
66B(0:2)
Max. Load
Units
pF
30
30
30
20
10
50
pF
pF
48MUSB Clock
48MDOT
pF
pF
REF Clock
pF
Notes:
27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
28. When crystal meets minimum 40: device series resistance specification.
29. Device is not affected, VTT_PWRGD# is ignored.
Rev 1.0,November 24, 2006
Page 17 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
