CY28339
Byte 2:PCI Clock Control Register (all bits are Read and Write functional)
Bit @Pup Name Description
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
REF REF Output Control. 0 = high strength, 1 = low strength.
PCI6 PCI6 Output Control. 0 = forced LOW, 1 = enabled
PCI5 PCI5 Output Control. 0 = forced LOW, 1 = enabled
PCI4 PCI4 Output Control. 0 = forced LOW, 1 = enabled
Reserved
PCI2 PCI2 Output Control. 0 = forced LOW, 1 = enabled
PCI1 PCI1 Output Control. 0 = forced LOW, 1 = enabled
PCI0 PCI0 Output Control. 0 = forced LOW, 1 = enabled
Byte 3: PCIF Clock and 48M Control Register (all bits are Read and Write functional)
Bit @Pup Name Description
7
6
5
4
3
2
1
0
1
1
0
1
1
1
1
1
DOT_48M DOT_48M Output Control. 0 = forced LOW, 1 = enabled
USB_48M USB_48M Output Control. 0 = forced LOW,1 = enabled
PCIF
PCI8
PCI7
PCIF
PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCIF Output Control. 0 = forced LOW, 1 = running
PCI_8 PCI_8 Output Control. 0 = forced LOW, 1 = running
PCI_7 PCI_7 Output Control. 0 = forced LOW, 1 = running
Byte 4: Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Name
Description
0
0
1
1
1
1
1
1
SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread).
Reserved. Set = 0.
6
5
3V66_0
3V66_1/VCH
3V66_5
3V66_0 Output Enable. 0 = disable, 1 = enabled
3V66_1/VCH Output Enable. 0 = disable, 1 = enabled
3V66_5 Output Enable. 0 = disable, 1 = enabled
66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled
66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled
66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled
4
3
2
19
1
18
0
66BUFF0/3V66_2
Byte 5:Clock Control Register (all bits are Read and Write functional)
Bit
7
@Pup
Name
Description
SS1 Spread Spectrum Control Bit.
0
1
0
0
0
0
0
0
6
SS0 Spread Spectrum Control Bit.
5
66IN to 66M delay Control MSB.
4
66IN to 66M delay Control LSB.
3
Reserved. Set = 0.
2
DOT_48M
USB_48M
DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%.
Reserved. Set = 0.
1
0
USB_48M edge rate control. When set to 1, the edge is slowed by 15%.
Byte 6: Silicon Signature Register[5] (all bits are Read-only)
Bit @Pup Name
Description
Rev 1.0,November 25, 2006
Page 4 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
