CY28329
VTTPWRGD# Timing Diagrams
GND VRM 5/12V
PWR_GD
VID [3:0]
BSEL [1:0]
VTTPWRGD FROM
VRM
VCC CPU CORE
VTTPWRGD
0.2–0.3 ms Wait for
delay
Sample
BSELS
VTTPWRGD#
VCC CLOCK GEN
State 1 State 2
State 3
State 0
CLOCK STATE
OFF
ON
CLOCK VCO
OFF
ON
CLOCK OUTPUTS
Figure 2. CPU Power BEFORE Clock Power
GND VRM 5/12V
PWRGD
VID [3:0]
BSEL [1:0]
PWRGD FROM
VRM
PWRGD# FROM
NPN
VCC CPU CORE
VTTPWRGD
Sample
BSELS
0.2–0.3 ms
delay
Wait for
VTTPWRGD#
VCC CLOCK GEN
CLOCK STATE
State 1
State 2
State 3
State 0
OFF
ON
ON
CLOCK VCO
OFF
CLOCK OUTPUTS
Figure 3. CPU Power AFTER Clock Power
Rev 1.0,November 24, 2006
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