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CY28301PVCT 参数 Datasheet PDF下载

CY28301PVCT图片预览
型号: CY28301PVCT
PDF下载: 下载PDF文件 查看货源
内容描述: 频率发生器英特尔(R )集成芯片组 [Frequency Generator for Intel(r) Integrated Chipset]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 13 页 / 168 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28301  
Pin Definitions  
Pin  
Type  
Pin Name  
Pin No.  
Pin Description  
REF/FS1  
56  
I/O  
Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output.  
This pin also serves as the select strap to determine the device operating  
frequency (as described in Table 5).  
X1  
X2  
2
3
I
Crystal Input: This pin has dual functions. It can be used as an external  
14.318-MHz crystal connection or as an external reference frequency  
input.  
O
Crystal Output: An input connection for an external 14.318-MHz crystal  
connection. If using an external reference, this pin must be left  
unconnected.  
PCI0  
11  
12  
13  
O
O
O
PCI Clock 0: 3.3V 33-MHz PCI clock output.  
PCI Clock 1: 3.3V 33-MHz PCI clock output.  
PCI1  
PCI2/SEL24_48MHz#  
PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This  
pin also serves as the select strap to determine the output frequency for  
24_48MHz output. Logic 1 = 24 MHz on pin 35.  
PCI3:7  
15, 16, 17, 19,  
20  
O
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be  
individually turned off via the SMBus interface.  
3V66_0:2  
48MHz/FS0  
6, 7, 8  
66-MHz Clock Output: 3.3V output clocks. The operating frequency is  
controlled by FS0:1 (see Table 5).  
34  
I/O  
48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread  
spectrum output. This pin also serves as the select strap to determine the  
device operating frequency (as described in Table 5.)  
24_48MHz  
PD#  
35  
22  
O
I
24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output.  
Power-down Input: LVTTL-compatible asynchronous input that places  
the device in power-down mode when held LOW.  
CPU0:1  
52, 51  
O
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output  
frequencies depending on the configuration of FS0:1. Voltage swing is set  
by VDDQ2.  
SDRAM0:11,  
SDRAM_F  
48, 47, 46, 44,  
43, 42, 40, 39,  
31, 30, 27, 26,  
38  
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The  
operating frequency is controlled by FS0:1 (see Table 5).  
APIC  
54  
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous  
with the PCI clock outputs. Voltage swing set by VDDQ2.  
SDATA  
SCLK  
24  
23  
I/O  
I
Data pin for SMBus circuitry.  
Clock pin for SMBus circuitry.  
VDD_REF,  
1, 9, 10, 18, 25,  
32, 37, 45, 33  
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI  
output buffers, reference output buffers, and 48-MHz output buffers.  
Connect to 3.3V.  
VDD_3V66,VDD_PCI,  
VDD_SDRAM,  
VDD_48MHz  
VDD_CPU,  
VDD_APIC  
53, 55  
P
2.5V Power Connection: Power supply for APIC and CPU output buffers.  
Connect to 2.5V.  
GND_REF,  
GND_3V66,  
GND_PCI,  
4, 5, 14, 21, 28,  
29, 41, 49, 50,  
36  
G
Ground Connections: Connect all ground pins to the common system  
ground plane.  
GND_SDRAM,  
GND_48MHZ,  
GND_CPU  
Rev 1.0,November 27, 2006  
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