CY2277A
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
CLOAD is used. Footprints can be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 PF.
In some cases, smaller value capacitors may be required.
• Thevalueofthe series terminating resistorsatisfies the followingequation, whereRtrace is theloaded characteristic impedance
ofthetrace,Rout istheoutputimpedanceoftheclockgenerator(specifiedinthedatasheet), andRseries istheseriesterminating
resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers
greater than 50: impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 PF– 22 PF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
Rev 1.0,November 25, 2006
Page 16 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
