A d v a n c e I n f o r m a t i o n
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
Data
Status
D
OUT
55h
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
March 31, 2005 S71GL032A_00_A0
S71GL032A Based MCPs
73
SPANSION [ SPANSION ]
