S34ML01G1 参数 Datasheet PDF下载

Da ta

Shee t

(Prelimi nar y)

6.10

Page Program Operation Timing with CE# Don’t Care

Figure 6.10

Page Program Operation Timing with CE# Don’t Care

CE# don’t care

CE#

CLE

ALE

WE#

RE#

I/Ox

80h

Col.

Add. 1

Col.

Add. 2

Row

Add. 1

Row

Add. 2

Row

Add.

3

Din

N

Din

N+1

Din

M

Din

P

Din

P+1

Din

R

10h

: Don’t Care

CE#

WE#

tCS

tWP

tCH

6.11

Page Program Operation with Random Data Input

Figure 6.11

Random Data Input

CLE

CE#

tWC

tWC

tWC

WE#

tADL

tADL

tWB

tPROG

tWHR

ALE

RE#

I/Ox

Col.

Add1

Col.

Add2

Row

Add1

Row

Add2

Row

Add3

80h

Serial

Data

Input Command

Din

N

Din

M

85h

Col.

Add1

Col.

Add2

Din

J

Din

K

Serial

Input

10h

Program

Command

70h

IO0

Column Address

Column Address

Random Data

Input Command

Column Address

Read

Status

Command

R/B#

Notes:

1. t

ADL

is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.

2. For EDC operation only one time Random Data Input is possible at same address.

September 6, 2012 S34ML01G1_04G1_10

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SLC NAND Flash Memory for Embedded

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