Da ta
Shee t
(Prelimi nar y)
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Table 13.1
Hardware Reset (RESET#)
Parameter
t
RPH
t
RP
t
RH
RESET# Low to CE# Low
RESET# Pulse Width
Time between RESET# (high) and CE# (low)
Description
Limit
Min
Min
Min
Time
35
200
200
Unit
µs
ns
ns
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 13.1
Reset Timings
RESET#
t
RP
t
RH
t
RPH
CE#
Note
The sum of t
RP
and t
RH
must be equal to or greater than t
RPH
.
Table 13.2
Power-Up Sequence Timings
Parameter
t
VCS
t
VIOS
t
RPH
t
RP
t
RH
V
CC
Setup Time to first access
V
IO
Setup Time to first access
RESET# Low to CE# Low
RESET# Pulse Width
Time between RESET# (high) and CE# (low)
Description
Limit
Min
Min
Min
Min
Min
Time
300
300
35
200
200
Unit
µs
µs
µs
ns
ns
Notes
1. V
IO
< V
CC
+ 200 mV.
2. V
IO
and V
CC
ramp must be in sync during power-up. If RESET# is not stable for 500 µs, the following conditions may occur: the device
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V
CC
power up current is 20 mA (RESET# =V
IL
).
Figure 13.2
Power-On Reset Timings
V
CC
V
IO
t
VIOS
t
VCS
t
RP
RESET#
t
RH
t
RPH
CE#
Note
The sum of t
RP
and t
RH
must be equal to or greater than t
RPH
.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
®
Flash Family
75
SPANSION [ SPANSION ]
