D a t a S h e e t
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL.
CE# is the power control and selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard mi-
croprocessor read cycles that assert valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains enabled for read access until the
command register contents are altered.
See Reading Array Data‚ on page 50 for more information. Refer to the AC Read-Only Oper-
ations table for timing specifications and to Figure 11, on page 78 for the timing diagram.
Refer to the DC Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask
ROM read operation. This mode provides faster read access speed for random locations within
a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by
the higher address bits A(max)–A3. Address bits A2–A0 in word mode (A2–A-1 in byte mode)
determine the specific word within a page. This is an asynchronous operation; the micropro-
cessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses
(as long as the locations specified by the microprocessor falls within that page) is equivalent
to tPACC. When CE# is de-asserted and reasserted for a subsequent access, the access time
is tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses”
constant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device
and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program a word or
byte, instead of four. The “Word Program Command Sequence” section has details on pro-
gramming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on
page 16, Table 4 on page 34, and Table 5 on page 37 indicate the address space that each
sector occupies.
Refer to the DC Characteristics table for the active current specification for the write mode.
The AC Characteristics section contains timing specification tables and timing diagrams for
write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. See Write Buffer‚ on page 14 for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of
two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster
manufacturing throughput at the factory.
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S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
