欢迎访问ic37.com |
会员登录 免费注册
发布采购

S29GL256M10TAIR10 参数 Datasheet PDF下载

S29GL256M10TAIR10图片预览
型号: S29GL256M10TAIR10
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有0.23微米的MirrorBit制程技术 [3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 160 页 / 4686 K
品牌: SPANSION [ SPANSION ]
 浏览型号S29GL256M10TAIR10的Datasheet PDF文件第100页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第101页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第102页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第103页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第105页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第106页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第107页浏览型号S29GL256M10TAIR10的Datasheet PDF文件第108页  
P r e l i m i n a r y  
reinitiated once the device has returned to the read mode, to ensure data  
integrity.  
Programming is allowed in any sequence of address locations and across sector  
boundaries. Programming to the same word address multiple times without in-  
tervening erases (incremental bit programming) requires a modified  
programming method. For such application requirements, please contact your  
local Spansion representative. Word programming is supported for backward  
compatibility with existing Flash driver software and for occasional writing of in-  
dividual words. Use of write buffer programming (see below) is strongly  
recommended for general programming use when more than a few words are to  
be programmed. The effective word programming time using write buffer pro-  
gramming is approximately four times shorter than the single word programming  
time.  
Any bit in a word cannot be programmed from “0” back to a “1.” Attempt-  
ing to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status  
bits to indicate the operation was successful. However, a succeeding read will  
show that the data is still “0.Only erase operations can convert a “0” to a “1.”  
Unlock Bypass Command Sequence  
The unlock bypass feature allows the system to program words to the device  
faster than using the standard program command sequence. The unlock bypass  
command sequence is initiated by first writing two unlock cycles. This is followed  
by a third write cycle containing the unlock bypass command, 20h. The device  
then enters the unlock bypass mode. A two-cycle unlock bypass mode command  
sequence is all that is required to program in this mode. The first cycle in this se-  
quence contains the unlock bypass program command, A0h; the second cycle  
contains the program address and data. Additional data is programmed in the  
same manner. This mode dispenses with the initial two unlock cycles required in  
the standard program command sequence, resulting in faster total programming  
time. Tables 31 and 32 show the requirements for the command sequence.  
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-  
pass Reset commands are valid. To exit the unlock bypass mode, the system  
must issue the two-cycle unlock bypass reset command sequence. The first cycle  
must contain the data 90h. The second cycle must contain the data 00h. The de-  
vice then returns to the read mode.  
Write Buffer Programming  
Write Buffer Programming allows the system write to a maximum of 16 words/32  
bytes in one programming operation. This results in faster effective programming  
time than the standard programming algorithms. The Write Buffer Programming  
command sequence is initiated by first writing two unlock cycles. This is followed  
by a third write cycle containing the Write Buffer Load command written at the  
Sector Address in which programming will occur. The fourth cycle writes the sec-  
tor address and the number of word locations, minus one, to be programmed. For  
example, if the system will program 6 unique address locations, then 05h should  
be written to the device. This tells the device how many write buffer addresses  
will be loaded with data and therefore when to expect the Program Buffer to Flash  
command. The number of locations to program cannot exceed the size of the  
write buffer or the operation will abort.  
The fifth cycle writes the first address location and data to be programmed. The  
write-buffer-page is selected by address bits A  
–A . All subsequent address/  
4
MAX  
104  
S29GLxxxM MirrorBitTM Flash Family  
S29GLxxxM_00A5 April 30, 2004  
 复制成功!