A d v a n c e I n f o r m a t i o n
Table 31. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
Command Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Data
Sixth
Addr Data
Addr Data Addr Data Addr Data
Addr
Data
Addr
Read (Note 6)
1
1
4
6
4
RA
RD
F0
Reset (Note 7)
XXX
AAA
AAA
AAA
Manufacturer ID
Device ID (Note 9)
Device ID(Note 10)
AA
AA
AA
555
555
555
55
55
55
AAA
AAA
AAA
90
90
90
X00
X02
X02
01
7E
X1C (Note 18) X1E (Note 18)
(Note 11)
Secured Silicon Sector Factory
Protect
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
X06
(Note 10)
00/01
Sector Group Protect Verify
(Note 12)
90 (SA)X04
88
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Write to Buffer (Note 13)
Program Buffer to Flash
3
4
3
1
3
6
6
1
1
1
AAA
AAA
AAA
SA
AA
AA
AA
29
AA
AA
AA
B0
30
98
555
555
555
55
55
55
AAA
AAA
SA
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
Write to Buffer Abort Reset (Note 14)
Chip Erase
AAA
AAA
AAA
XXX
XXX
AA
555
555
555
55
55
55
AAA
AAA
AAA
F0
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 4 on page 18 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don’t care.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read mode.
7. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in
autoselect mode, or if DQ5 goes high while device is providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect Command Sequence on
page 44e or more information.
9. For S29GL064A and S29GL032A Device ID must be read in three cycles.
10. For S29GL016A, Device ID must be read in one cycle.
11. Refer to Table 15 on page 31, for data indicating Secured Silicon Sector factory protect status.
12. Data is 00h for an unprotected sector group and 01h for a protected sector group.
13. Total number of cycles in command sequence is determined by number of bytes written to write buffer. Maximum number of cycles in
command sequence is 37, including Program Buffer to Flash command.
14. Command sequence resets device for next command after aborted write-to-buffer operation.
15. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command
is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend mode.
17. Command is valid when device is ready to read array data or when device is in autoselect mode.
18. Refer to Table 15 on page 31, for individual Device IDs per device density and model number.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
55
SPANSION [ SPANSION ]
