A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on
page 39).
2. Illustration shows device in word mode.
Figure 19. Chip/Sector Erase Operation Timings
t
t
WC
RC
Addresses
PA
PA
PA
PA
t
t
ACC
t
AH
CPH
t
CE
CE#
OE#
t
CP
t
OE
t
GHWL
t
SR/W
t
WP
t
t
WE#
Data
DF
t
WDH
DS
t
OH
t
DH
Valid
In
Valid
Out
Valid In
Valid Out
Figure 20. Back to Back Read/Write Cycle Timing
56
S29AL032D
S29AL032D_00_A3 June 13, 2005
SPANSION [ SPANSION ]
