A d v a n c e I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
NOTE: See Table 17 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations. Table 17 on page 38 shows the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that
a hardware reset during the chip erase operation immediately terminates the operation. The
Chip Erase command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#.
See Write Operation Status on page 39 for information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading array data and addresses are no longer
latched.
Figure 5, on page 36 illustrates the algorithm for the erase operation. See Erase/Program
Operations on page 54 for parameters, and to Figure 19, on page 56 for timing diagrams.
34
S29AL032D
S29AL032D_00_A3 June 13, 2005
SPANSION [ SPANSION ]
