A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further detail.
Table 1. S29AL032D Device Bus Operations
DQ8–DQ15 (Note 6)
WP#(Note 6)/
ACC
Addresses
(Note 3)
DQ0–
DQ7
Operation
CE#
OE# WE# RESET#
BYTE#
= V
BYTE# = V
IL
IH
OUT
Read
L
L
L
H
L
H
H
L/H
A
A
D
D
IN
OUT
DQ8–DQ14 =
High-Z, DQ15 =
A-1
Write (Note 1)
H
(Note 4)
(Note 5) (Note 5)
IN
Accelerated Program
(Note 6)
L
H
X
L
H
V
A
(Note 5) (Note 5)
HH
IN
V
V
CC
0.3 V
CC
0.3 V
Standby
X
H
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 3)
L
L
H
H
X
L
L
V
V
V
L/H
(Note 5)
(Note 5)
X
X
X
X
ID
ID
ID
Sector Unprotect
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
(Note 4)
(Note 4)
Temporary Sector
Unprotect
X
X
A
(Note 5) (Note 5)
High-Z
IN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT
= Data Out
Notes:
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See
2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
3. The sector protect and sector unprotect functions may also be implemented via programming equipment.
4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected.
5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
6. Models 03, 04 only
Word/Byte Configuration (Models 03, 04 Only)
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0
are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–
DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and
the DQ15 pin is used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V . CE# is
IL
the power control and selects the device. OE# is the output control and gates array data to the
output pins. WE# should remain at V . The BYTE# pin determines whether the device outputs
IH
array data in words or bytes.
June 13, 2005 S29AL032D_00_A3
S29AL032D
11
SPANSION [ SPANSION ]
