Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
0.7
32
18
18
36
19
7.5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Word Programming Time
µs
µs
s
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
Chip Programming Time
(Note 3)
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 10,000 cycles, checkerboard data
pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables 2–3 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Unit
pF
pF
pF
pF
pF
pF
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
TSOP
BGA
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
TSOP
BGA
CIN2
Control Pin Capacitance
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
53
S29AL016M
S29AL016M_00A4 April 21, 2004
SPANSION [ SPANSION ]
