Test Conditions
Table 13. Test Specifications
3.3 V
Test Condition
Output Load
90, 100
Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
6.2 kΩ
L
0.0 or VCC
Input timing measurement
reference levels
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VCC
0.5 VCC
0.5 VCC
Input
Measurement Level
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
April 21, 2004 S29AL016M_00A4
S29AL016M
42
SPANSION [ SPANSION ]
