D a t a S h e e t
AC Characteristics
Table 9. Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note )
tREADY
20
µs
Max
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note )
tREADY
500
ns
tRP
tRH
RESET# Pulse Width
500
50
20
0
RESET# High Time Before Read (See Note )
Min
tRPD RESET# Low to Standby Mode
tRB RY/BY# Recovery Time
µs
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
Figure 14. RESET# Timings
June 16, 2005 S29AL008D_00A3
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