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S29AL008D70TAI020 参数 Datasheet PDF下载

S29AL008D70TAI020图片预览
型号: S29AL008D70TAI020
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 3.0伏只引导扇区闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 55 页 / 1519 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t  
The device enters the CMOS standby mode when the CE# and RESET# pins are  
both held at V  
0.3 V. (Note that this is a more restricted voltage range than  
V .) If CE# and RESET# are held at V , but not within V 0.3 V, the device  
is in the standby mode, but the standby current is greater. The device requires  
CC  
IH  
IH  
CC  
standard access time (t ) for read access when the device is in either of these  
CE  
standby modes, before it is ready to read data.  
If the device is deselected during erasure or programming, the device draws ac-  
tive current until the operation is completed.  
In the DC Characteristics table, I  
specification.  
and I  
represents the standby current  
CC4  
CC3  
Automatic Sleep Mode  
The automatic sleep mode minimizes Flash device energy consumption. The de-  
vice automatically enables this mode when addresses remain stable for t + 30  
ACC  
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control  
signals. Standard address access timings provide new data when addresses are  
changed. While in sleep mode, output data is latched and always available to the  
system. I  
in the DC Characteristics table represents the automatic sleep mode  
CC4  
current specification.  
RESET#: Hardware Reset Pin  
The RESET# pin provides a hardware method of resetting the device to reading  
array data. When the RESET# pin is driven low for at least a period of t , the  
RP  
device immediately terminates any operation in progress, tristates all output  
pins, and ignores all read/write commands for the duration of the RESET# pulse.  
The device also resets the internal state machine to reading array data. The op-  
eration that was interrupted should be reinitiated once the device is ready to  
accept another command sequence, to ensure data integrity.  
Current is reduced for the duration of the RESET# pulse. When RESET# is held  
at V ±0.3 V, the device draws CMOS standby current (I  
). If RESET# is held  
SS  
CC4  
at V but not within V ±0.3 V, the standby current is greater.  
IL  
SS  
The RESET# pin may be tied to the system reset circuitry. A system reset would  
thus also reset the Flash memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-  
mains a 0 (busy) until the internal reset operation is complete, which requires a  
time of t  
(during Embedded Algorithms). The system can thus monitor RY/  
READY  
BY# to determine whether the reset operation is complete. If RESET# is asserted  
when a program or erase operation is not executing (RY/BY# pin is 1), the reset  
operation is completed within a time of t  
(not during Embedded Algorithms).  
READY  
The system can read data t  
after the RESET# pin returns to V .  
IH  
RH  
Refer to AC Characteristics, on page 38 for RESET# parameters and to Figure  
14, on page 39 for the timing diagram.  
Output Disable Mode  
When the OE# input is at V , output from the device is disabled. The output pins  
IH  
are placed in the high impedance state.  
June 16, 2005 S29AL008D_00A3  
S29AL008D  
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