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AM29F010B-90JF 参数 Datasheet PDF下载

AM29F010B-90JF图片预览
型号: AM29F010B-90JF
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128千×8位) CMOS 5.0伏只,统一部门快闪记忆体 [1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory]
分类和应用:
文件页数/大小: 33 页 / 1007 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash  
memory organized as 131,072 bytes. The Am29F010B  
is offered in 32-pin PDIP, PLCC and TSOP packages.  
The byte-wide data appears on DQ0-DQ7. The de-  
vice is designed to be programmed in-system with the  
automatically times the program pulse widths and  
verifies proper cell margin.  
Device erasure occurs by executing the erase com-  
mand sequence. This invokes the Embedded Erase  
algorithm—an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper cell margin.  
standard system 5.0 Volt V supply. A 12.0 volt V is not  
CC  
PP  
required for program or erase operations. The device can  
also be programmed or erased in standard EPROM  
programmers.  
This device is manufactured using AMD’s 0.32 µm pro-  
cess technology, and offers all the features and benefits  
of the Am29F010 and Am29F010A.  
The host system can detect whether a program or  
erase operation is complete by reading the DQ7 (Data#  
Polling) and DQ6 (toggle) status bits. After a program  
or erase cycle has been completed, the device is ready  
to read array data or accept another command.  
The standard device offers access times of 45, 55, 70,  
90, and 120 ns, allowing high-speed microprocessors  
to operate without wait states. To eliminate bus conten-  
tion the device has separate chip enable (CE#), write  
enable (WE#) and output enable (OE#) controls.  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is erased  
when shipped from the factory.  
The device requires only a single 5.0 volt power sup-  
ply for both read and write functions. Internally  
generated and regulated voltages are provided for the  
program and erase operations.  
The hardware data protection measures include a  
low V detector automatically inhibits write operations  
CC  
during power transitions. The hardware sector protec-  
tion feature disables both program and erase operations  
in any combination of the sectors of memory, and is im-  
plemented using standard EPROM programmers.  
The device is entirely command set compatible with the  
JEDEC single-power-supply Flash standard. Com-  
mands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state machine that  
controls the erase and programming circuitry. Write  
cycles also internally latch addresses and data needed  
for the programming and erase operations. Reading  
data out of the device is similar to reading from other  
Flash or EPROM devices.  
The system can place the device into the standby mode.  
Power consumption is greatly reduced in this mode.  
AMD’s Flash technology combines years of Flash  
memory manufacturing experience to produce the  
highest levels of quality, reliability, and cost  
effectiveness. The device electrically erases all bits  
within a sector simultaneously via Fowler-Nordheim  
tunneling. The bytes are programmed one byte at a  
time using the EPROM programming mechanism of hot  
electron injection.  
Device programming occurs by executing the program  
command sequence. This invokes the Embedded Pro-  
gram algorithm—an internal algorithm that  
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Am29F010B  
Am29F010B_00_C7 October 31, 2006