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AM29F010B70EC 参数 Datasheet PDF下载

AM29F010B70EC图片预览
型号: AM29F010B70EC
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128千×8位) CMOS 5.0伏只,统一部门快闪记忆体 [1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory]
分类和应用:
文件页数/大小: 35 页 / 821 K
品牌: SPANSION [ SPANSION ]
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DEVICE BUS OPERATIONS  
This section describes the requirements and use of the  
device bus operations, which are initiated through the  
internal command register. The command register itself  
does not occupy any addressable memory location.  
The register is composed of latches that store the com-  
mands, along with the address and data information  
needed to execute the command. The contents of the  
register serve as inputs to the internal state machine.  
The state machine outputs dictate the function of the  
device. The appropriate device bus operations table  
lists the inputs and control levels required, and the re-  
sulting output. The following subsections describe  
each of these operations in further detail.  
Table 1. Am29F010B Device Bus Operations  
Addresses  
(Note 1)  
Operation  
CE#  
OE#  
L
WE#  
H
DQ0–DQ7  
DOUT  
Read  
L
AIN  
AIN  
X
Write  
L
H
L
DIN  
Standby  
VCC ± 0.5 V  
X
X
High-Z  
High-Z  
High-Z  
Output Disable  
Hardware Reset  
L
H
H
X
X
X
X
X
Legend:  
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out  
Notes:  
1. Addresses are A16:A0.  
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-  
tection/Unprotection” section.  
Requirements for Reading Array Data  
Writing Commands/Command Sequences  
To read array data from the outputs, the system must  
drive the CE# and OE# pins to VIL. CE# is the power  
control and selects the device. OE# is the output con-  
trol and gates array data to the output pins. WE#  
should remain at VIH.  
To write a command or command sequence (which in-  
cludes programming data to the device and erasing  
sectors of memory), the system must drive WE# and  
CE# to VIL, and OE# to VIH.  
An erase operation can erase one sector, multiple sec-  
tors, or the entire device. The Sector Address Tables  
indicate the address space that each sector occupies.  
A “sector address” consists of the address bits required  
to uniquely select a sector. See the “Command Defini-  
tions” section for details on erasing a sector or the  
entire chip.  
The internal state machine is set for reading array data  
upon device power-up, or after a hardware reset. This  
ensures that no spurious alteration of the memory con-  
tent occurs during the power transition. No command is  
necessary in this mode to obtain array data. Standard  
microprocessor read cycles that assert valid addresses  
on the device address inputs produce valid data on the  
device data outputs. The device remains enabled for  
read access until the command register contents are  
altered.  
After the system writes the autoselect command se-  
quence, the device enters the autoselect mode. The  
system can then read autoselect codes from the inter-  
nal register (which is separate from the memory array)  
on DQ7–DQ0. Standard read cycle timings apply in this  
mode. Refer to the “Autoselect Mode” and “Autoselect  
Command Sequence” sections for more information.  
See “Reading Array Data” for more information. Refer  
to the AC Read Operations table for timing specifica-  
tions and to the Read Operations Timings diagram for  
the timing waveforms. ICC1 in the DC Characteristics  
table represents the active current specification for  
reading array data.  
ICC2 in the DC Characteristics table represents the ac-  
tive current specification for the write mode. The “AC  
Characteristics” section contains timing specification  
tables and timing diagrams for write operations.  
November 18, 2002  
Am29F010B  
9