D A T A S H E E T
dresses are changed. While in sleep mode, output
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
data is latched and always available to the system.
ICC5 in the DC Characteristics table represents the
automatic sleep mode current specification.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
ICC4 in the DC Characteristics table represents the
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 14 for the
timing diagram.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current will
be greater.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
Table 2. Device Bank Divisions
Bank 1
Bank 2
Sector Sizes
Device
Part Number
Megabits
Sector Sizes
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Fifty-six
64 Kbyte/32 Kword
Am29DL322G
4 Mbit
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
Am29DL323G
Am29DL324G
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
thirty-one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
12
Am29DL32xG
25686B10 December 4, 2006
SPANSION [ SPANSION ]
