Table 13. Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Addr Addr Data
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Addr
Addr Data Addr Data
Data
Addr Data
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
555
AAA
555
AAA
555
RD
F0
Word
Byte
2AA
555
2AA
555
2AA
555
2AA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90 (BA)X00 01
(BA)X01
Word
Byte
(BA)X0E
0A
(BA)X0F
(BA)X1E
00/
01
Device ID (Note 9)
90
7E
(BA)X02
(BA)X03
(BA)X06
(SA)X02
(BA)X1C
Word
Byte
SecSi™ Sector Factory
Protect (Note 10)
90
82/02
Sector/Sector Block
Protect Verify
(Note 11)
Word
4
AA
55
90
00/01
Byte
AAA
555
(BA)AAA
(SA)X04
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
2AA
555
2AA
555
PA
555
AAA
555
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
AA
AA
AA
AA
55
55
55
55
88
90
A0
20
XXX
PA
00
AAA
555
AAA
555
PD
AAA
555
AAA
555
Unlock Bypass
AAA
XXX
AAA
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
2
2
A0
90
PD
00
BA
555
AAA
555
AAA
BA
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
55
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
10
30
555
AAA
Word
2AA
55
Sector Erase
Byte
SA
AAA
AAA
555
Erase Suspend (Note 14)
Erase Resume (Note 15)
1
1
B0
30
BA
Word
CFI Query (Note 16)
Byte
55
1
98
AA
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
Notes:
1. See Table 1 for description of bus operations.
9. The device ID must be read across three cycles. The device ID is
00h for bottom boot devices, and 01h for top boot devices.
2. All values are in hexadecimal.
10. The data is 82h for factory locked and 02h for not factory locked.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The data is 00h for an unprotected sector/sector block and 01h for
a protected sector/sector block.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
13. The Unlock Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
6. No unlock or command cycles required when bank is reading
array data.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
28
Am29DL320G
September 27, 2004
SPANSION [ SPANSION ]
