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AM29DL320GT70WDFN 参数 Datasheet PDF下载

AM29DL320GT70WDFN图片预览
型号: AM29DL320GT70WDFN
PDF下载: 下载PDF文件 查看货源
内容描述: 对于涉及TSOP封装的新设计, S29JL032H将取代Am29DL320G ,是厂家推荐的迁移路径。 [For new designs involving TSOP packages, S29JL032H supercedes Am29DL320G and is the factory-recommended migration path.]
分类和应用: 闪存内存集成电路
文件页数/大小: 58 页 / 1241 K
品牌: SPANSION [ SPANSION ]
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Table 14 shows the outputs for Toggle Bit I on DQ6.  
Figure 7 shows the toggle bit algorithm. Figure 23 in  
the “AC Characteristics” section shows the toggle bit  
timing diagrams. Figure 24 shows the differences be-  
tween DQ2 and DQ6 in graphical form. See also the  
subsection on DQ2: Toggle Bit II.  
RY/BY#: Ready/Busy#  
The RY/BY# is a dedicated, open-drain output pin  
which indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after  
the rising edge of the final WE# pulse in the command  
sequence. Since RY/BY# is an open-drain output, sev-  
eral RY/BY# pins can be tied together in parallel with a  
pull-up resistor to VCC  
.
If the output is low (Busy), the device is actively eras-  
ing or programming. (This includes programming in  
the Erase Suspend mode.) If the output is high  
(Ready), the device is in the read mode, the standby  
mode, or one of the banks is in the erase-sus-  
pend-read mode.  
START  
Read DQ7–DQ0  
Table 14 shows the outputs for RY/BY#.  
Read DQ7–DQ0  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or com-  
plete, or whether the device has entered the Erase  
Suspend mode. Toggle Bit I may be read at any ad-  
dress, and is valid after the rising edge of the final  
WE# pulse in the command sequence (prior to the  
program or erase operation), and during the sector  
erase time-out.  
No  
Toggle Bit  
= Toggle?  
Yes  
No  
During an Embedded Program or Erase algorithm op-  
eration, successive read cycles to any address cause  
DQ6 to toggle. The system may use either OE# or  
CE# to control the read cycles. When the operation is  
complete, DQ6 stops toggling.  
DQ5 = 1?  
Yes  
Read DQ7–DQ0  
Twice  
After an erase command sequence is written, if all sectors  
selected for erasing are protected, DQ6 toggles for approxi-  
mately 100 µs, then returns to reading array data. If not all  
selected sectors are protected, the Embedded Erase algo-  
rithm erases the unprotected sectors, and ignores the se-  
lected sectors that are protected.  
Toggle Bit  
= Toggle?  
No  
The system can use DQ6 and DQ2 together to determine  
whether a sector is actively erasing or is erase-suspended.  
When the device is actively erasing (that is, the Embedded  
Erase algorithm is in progress), DQ6 toggles. When the de-  
vice enters the Erase Suspend mode, DQ6 stops toggling.  
However, the system must also use DQ2 to determine  
which sectors are erasing or erase-suspended. Alterna-  
tively, the system can use DQ7 (see the subsection on  
DQ7: Data# Polling).  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
Note: The system should recheck the toggle bit even if DQ5  
= “1” because the toggle bit may stop toggling as DQ5  
changes to “1.” See the subsections on DQ6 and DQ2 for  
more information.  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 1 µs after the program  
command sequence is written, then returns to reading  
array data.  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling once the Embedded Pro-  
gram algorithm is complete.  
Figure 7. Toggle Bit Algorithm  
30  
Am29DL320G  
September 27, 2004