For new designs involving TSOP packages, S29JL032H supersedes Am29DL320G and is the factory-recom-
mended migration path. Please refer to the S29JL032H Datasheet for specifications and ordering information.
For new designs involving Fine-pitch BGA (FBGA) packages, S29PL032J supersedes Am29DL320G and is
the factory-recommended migration path. Please refer to the S29PL032J Datasheet for specifications and
ordering information.
Am29DL320G
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
■
Minimum 1 million write cycles guaranteed per sector
■
■
Simultaneous Read/Write operations
20 year data retention at 125°C
— Reliable operation for the life of the system
— Data can be continuously read from one bank while
executing erase/program functions in another bank
SOFTWARE FEATURES
— Zero latency between read and write operations
Flexible BankTM architecture
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Read may occur in any of the three banks not being
written or erased.
— Eases historical sector erase flash limitations
— Four banks may be grouped by customer to achieve
desired bank divisions.
■
■
Supports Common Flash Memory Interface (CFI)
■
256-byte SecSi™ (Secured Silicon) Sector
Erase Suspend/Erase Resume
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
— Suspends erase operations to allow reading from
other sectors in the same bank
■
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
— Customer lockable: One time programmable. Once
Unlock Bypass Program command
locked, data cannot be changed.
— Reduces overall programming time when issuing
multiple program command sequences
■
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
HARDWARE FEATURES
■
Any combination of sectors can be erased
Package options
— 63-ball FBGA
— 48-ball FBGA
— 48-pin TSOP
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
— 64-ball Fortified BGA
■
■
■
Top or bottom boot blocks
WP#/ACC input pin
Manufactured on 0.17 µm process technology
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Acceleration (ACC) function accelerates program
timing
PERFORMANCE CHARACTERISTICS
■
Sector protection
■
High performance
— Access time as fast 70 ns
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Program time: 4 µs/word typical utilizing Accelerate
function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Publication# 25769 Rev: C Amendment/ 2
Issue Date: September 27, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
SPANSION [ SPANSION ]
