D A T A S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDEC Std Description
Test Setup
70
70
70
70
30
16
16
80
80
80
80
30
16
16
90
90
90
90
40
16
16
120 Unit
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tRC Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
120
120
120
50
ns
ns
ns
ns
ns
ns
tACC Address to Output Delay
tCE Chip Enable to Output Delay
tOE Output Enable to Output Delay
CE#, OE# = VIL
OE# = VIL
tDF Chip Enable to Output High Z (Notes 1, 3)
tDF Output Enable to Output High Z (Notes 1, 3)
16
16
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 16 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE# high to
the data bus driven to VCC/2 is taken as tDF.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
38
Am29DL16xD
21533E6 February 26, 2009
SPANSION [ SPANSION ]
