D A T A S H E E T
TEST CONDITIONS
Table 16. Test Specifications
3.3 V
Test Condition
70, 80
90, 120 Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
30
100
pF
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
C
L
6.2 kΩ
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key To Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
February 26, 2009 21533E6
Am29DL16xD
37
SPANSION [ SPANSION ]
