D A T A S H E E T
INPUT/OUTPUT DESCRIPTIONS
Amax–A0
=
Address inputs
Amax = A22 (128 Mb) or A21 (64 Mb)
AVD#
=
Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(Amax–A0).
DQ15–DQ0 = Data input/output
CE#
OE#
WE#
=
Chip Enable input. Asynchronous
relative to CLK for the Burst mode.
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched.
=
Output Enable input. Asynchronous
relative to CLK for the Burst mode.
=
=
Write Enable input.
High = device ignores address inputs
V
V
V
Device Power Supply
(1.65 – 1.95 V).
RESET#
WP#
=
=
Hardware reset input. Low = device
resets and returns to reading array
data
CC
=
Input & Output Buffer Power Supply
(1.65 – 1.95 V).
IO
Hardware write protect input. At V ,
IL
disables program and erase functions
in the four highest and four lowest
=
=
=
Ground
SS
NC
No Connect; not connected internally
Ready output;
sectors. At V , does not protect any
IH
sectors.
RDY
ACC
=
At V , accelerates programming;
automatically places device in unlock
HH
In Synchronous Mode, indicates the
status of the Burst read.
bypass mode. At V , locks all sectors.
IL
Low = data invalid. High = data valid.
Should be at V for all other
IH
conditions.
In Asynchronous Mode, indicates the
status of the internal program and
erase function.
LOGIC SYMBOL
Low = program/erase in progress.
23 or 22
High Impedance = program/erase
completed.
Amax–A0
16
DQ15–DQ0
CLK
WP#
CLK
=
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
9
SPANSION [ SPANSION ]
