D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Part Number
Burst Frequency
Speed Option
Max Initial Synchronous Access Time, ns (T
IACC
)
Reduced Wait-state Handshaking; Even Address
Max Initial Synchronous Access Time, ns (T
IACC
)
Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking
Max Burst Access Time, ns (T
BACC
)
Max Asynchronous Access Time, ns (T
ACC
)
Max CE# Access Time, ns (T
CE
)
Max OE# Access Time, ns (T
OE
)
11
13.5
V
CC
, V
IO
= 1.65
–
1.95 V
Am29BDS128H/Am29BDS640H
66 MHz
E8, E9
56
54 MHz
D8, D9
69
71
11
50
87.5
13.5
55
Note:
Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous
accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC
Characteristics section of this data sheet for full specifications.
BLOCK DIAGRAM
V
CC
V
SS
V
IO
RDY
Buffer
RDY
Erase Voltage
Generator
WE#
RESET#
WP#
ACC
State
Control
Command
Register
Input/Output
Buffers
DQ15–DQ0
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
Timer
Address Latch
V
CC
Detector
Y-Gating
X-Decoder
Cell Matrix
AVD#
CLK
Burst
State
Control
Burst
Address
Counter
Amax–A0
Note:
A
max
= A22 (128 Mb) or A21 (64 Mb)
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
5
SPANSION [ SPANSION ]
