D A T A S H E E T
BAA# Low enables the burst mode
Flash device to read from the next
word when gated with the rising edge
of the clock. Data becomes available
PIN CONFIGURATION
A0–A18
=
19 addresses
DQ0–DQ15 = 16 data inputs/outputs
t
ns of burst access time after the
BACC
CE#
OE#
WE#
=
=
=
Chip Enable Input. This signal shall be
asynchronous relative to CLK for the
burst mode.
rising edge of the clock
BAA # High prevents the rising edge of
the clock from advancing the data to
the next word output. The output data
remains unchanged.
Output Enable Input. This signal shall
be asynchronous relative to CLK for
the burst mode.
IND#
=
=
Highest burst counter address
reached. IND# is low at the end of a
32-word burst sequence (when word
Da + 31 is output). The output will
wrap around to Da on the next CLK
cycle (with BAA# low).
Write enable. This signal shall be
asynchronous relative to CLK for the
burst mode.
V
=
=
Device ground
SS
NC
No connect. Pin not connected
internally
RESET#
Hardware reset input
Note: The address, data, and control signals (RY/BY#, LBA,
BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant.
RY/BY#
CLK
=
=
Ready Busy output
Clock Input that can be tied to the
system or microprocessor clock and
provides the fundamental timing and
internal operating frequency. CLK
latches input addresses in conjunction
with LBA# input and increments the
burst address with the BAA# input.
LOGIC SYMBOL
19
A0–A18
16
DQ0–DQ15
CLK
LBA#
=
Load Burst Address input. Indicates
that the valid address is present on the
address inputs.
CE#
OE#
LBA# Low at the rising edge of the
clock latches the address on the
address inputs into the burst mode
Flash device. Data becomes available
IND#
WE#
RESET#
LBA#
RY/BY#
t
ns of initial access time after the
PACC
rising edge of the same clock that
latches the address.
BAA#
LBA# High indicates that the address
is not valid
BAA#
=
Burst Address Advance input.
Increments the address during the
burst mode operation
6
Am29BL802C
22371C7 November 3, 2006
SPANSION [ SPANSION ]
