DATA SHEET
Am29BL802C
8 Megabit (512 K x 16-Bit)
CMOS 3.0 Volt-only Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 32 words sequential with wrap around (linear
■ Embedded Algorithms
32), bottom boot
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ One 8 Kword, two 4 Kword, one 48 Kword, three
64 Kword, and two 128 Kword sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Minimum 100,000 erase cycle guarantee
per sector
■ 20-year data retention
■ Read access times
■ Compatibility with JEDEC standards
Burst access times as fast as 17 ns at industrial
temperature range (18 ns at extended
temperature range)
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
Initial/random access times as fast as 65 ns
■ Alterable burst length via BAA# pin
■ Power dissipation (typical)
— Backward-compatible with AMD Am29LV and
Am29F flash memories: powers up in
asynchronous mode for system boot, but can
immediately be placed into burst mode
— Burst Mode Read: 15 mA @ 25 MHz,
20 mA @ 33 MHz, 25 mA @ 40 MHz
■ Data# Polling and toggle bits
— Program/Erase: 20 mA
— Provides a software method of detecting
program or erase operation completion
— Standby mode, CMOS: 3 µA
■ 5 V-tolerant data, address, and control signals
■ Sector Protection
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
— Implemented using in-system or via
programming equipment
■ Erase Suspend/Erase Resume
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■ Package Option
— 56-pin SSOP
Publication# 22371 Rev: C Amendment: 7
Issue Date: November 3, 2006
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
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