D A T A S H E E T
the device. The first burst data is available after the
initial access time (t ) from the rising edge of the
CLK that loads the burst address. After the initial
Requirements for Reading Array Data
Array in Asynchronous (Non-Burst) Mode
To read array data from the outputs, the system must
IACC
access, subsequent burst data is available t
each rising edge of CLK.
after
BACC
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
The device increments the address at each rising edge
of the clock cycles while BAA# is asserted low. The 5-
bit burst address counter is set to 00000b at the
starting address. When the burst address counter is
reaches 11111b, the device outputs the last word in the
burst sequence, and outputs a low on IND#. If the
system continues to assert BAA#, on the next CLK the
device will output the data for the starting address—the
burst address counter will have “wrapped around” to
00000b. For example, if the initial address is xxxx0h,
the data order will be 0-1-2-3.....28-29-30-31-0-1...; if
the initial address is xxxx2h, the data order will be 2-3-
4-5.....28-29-30-31-0-1-2-3...; if the initial address is
xxxx8h, the data order will be 8-9-10-11.....30-31-0-1-
2-3-4-5-6-7-8-9....; and so on. Data will be repeated if
more than 32 clocks are supplied, and BAA# remains
asserted low.
main at V .
IH
Address access time (t
) is equal to the delay from
ACC
stable addresses to valid output data. The chip enable
access time (t ) is the delay from the stable
CE
addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
t
–t time).
ACC OE
The internal state machine is set for reading array
data in the upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
A burst mode read operation is terminated using one of
three methods:
— In the first method, CE# is asserted high. The
device in this case remains in burst mode;
asserting LBA# low terminates the previous
burst read cycle and starts a new burst read
cycle with the address that is currently valid.
See “Reading Array Data in Non-burst Mode” for more
information. Refer to the AC Read Operations table for
timing specifications and to Figure 15 for the timing di-
agram. I
in the DC Characteristics table represents
CC1
— In the second method, the Burst Disable
command sequence is written to the device. The
device halts the burst operation and returns to
the asynchronous mode.
the active current specification for reading array data.
Requirements for Reading Array Data in
Synchronous (Burst) Mode
The device offers fast 32-word sequential burst reads
and is used to support microprocessors that implement
an instruction prefetch queue, as well as large data
transfers during system configuration.
— In the third method, RESET# is asserted low. All
opertations are immediately terminated, and the
device will revert to the asynchronous mode.
Note that writing the reset command will not terminate
the burst mode.
Three additional pins—Load Burst Address (LBA#),
Burst Address Advance (BAA#), and Clock (CLK)—
allow interfacing to microprocessors and microcontrol-
lers with minimal glue logic. Burst mode read is a syn-
chronous operation tied to the rising edge of CLK. CE#,
OE#, and WE# are asynchronous (relative to CLK).
Burst Suspend/Burst Resume Operations
The device offers Burst Suspend and Burst Resume
operations. When both OE# and BAA# are taken high,
the device removes (“suspends”) the data from the
outputs (because OE# is high), but “holds” the data
internally. The device resumes burst operation when
either OE# and/or BAA# is asserted low. Asserting the
OE# only causes the device to present the same data
that was held during the Burst Suspend operation. As
long as BAA# is high, the device will continue to output
that word of data. Asserting both OE# and BAA# low
resumes the burst operation, and on the next rising
edge of CLK, increments the counter and outputs the
next word of data.
When the device is in asynchronous mode (after
power-up or RESET# pulse), any signals on the CLK,
LBA#, and BAA# inputs are ignored. The device oper-
ates as a conventional flash device, as described in the
previous section.
To enable burst mode operation, the system must issue
the Burst Mode Enable command sequence (see Table
4). After the device has entered the burst mode, the
system must assert Load Burst Address (LBA#) low for
one clock period, which loads the starting address into
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