D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
tRP
Max
Min
Min
500
500
50
ns
ns
ns
RESET# Pulse Width
RESET# High Time Before Read (See
Note)
tRH
tRPD RESET# Low to Standby Mode
tRB RY/BY# Recovery Time
Min
Min
20
0
µs
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 17. RESET# Timings
32
Am29BL802C
22371C7 November 3, 2006
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