D A T A S H E E T
The system can determine the status of the erase op-
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for informa-
tion on these status bits.)
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these status
bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses
are no longer latched.
Figure 6 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 19 for
timing diagrams.
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 19 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements for the sector erase command sequence.
START
Write Erase
Command Sequence
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Data Poll
from System
Embedded
Erase
algorithm
in progress
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 4 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. The Erase Suspend command has a different
effect depending on whether the Flash device is in
Asynchronous Mode or Burst Mode.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Asynchronous Mode
The Erase Suspend command is only valid when the
Flash device is in Asynchronous Mode. During Erase
Suspend operation Asynchronous read/program oper-
ations behave normally in non-erasing sectors. How-
ever, Erase Suspend operation prevents the Flash
18
Am29BL802C
22371C7 November 3, 2006
SPANSION [ SPANSION ]
