D A T A S H E E T
LBA#, and BAA# inputs are ignored. The device oper-
Requirements for Reading Array Data
Array in Asynchronous (Non-Burst) Mode
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
ates as a conventional flash device, as described in the
previous section.
To enable burst mode operation, the system must issue
the Burst Mode Enable command sequence (see
Table 8). After the device has entered the burst mode,
the system must assert Load Burst Address (LBA#) low
for one clock period, which loads the starting address
into the device. The first burst data is available after the
initial access time (tIACC) from the rising edge of the
CLK that loads the burst address. After the initial
access, subsequent burst data is available tBACC after
each rising edge of CLK.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable
addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
The device increments the address at each rising edge
of the clock cycles while BAA# is asserted low. The 5-
bit burst address counter is set to 00000b at the
starting address. When the burst address counter is
reaches 11111b, the device outputs the last word in the
burst sequence, and outputs a low on IND#. If the
system continues to assert BAA#, on the next CLK the
device outputs the data for the starting address—the
burst address counter is “wrapped around” to 00000b.
For example, if the initial address is xxxx0h, the data
order is 0-1-2-3…28-29-30-31-0-1…; if the initial
address is xxxx2h, the data order is 2-3-4-5…28-29-
30-31-0-1-2-3…; if the initial address is xxxx8h, the
data order is 8-9-10-11…30-31-0-1-2-3-4-5-6-7-8-9…;
and so on. Data is repeated if more than 32 clocks are
supplied, and BAA# remains asserted low.
The internal state machine is set for reading array
data in the upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data in Non-burst Mode” for more
information. Refer to the AC Read Operations table for
timing specifications and to Figure 15 for the timing di-
agram. ICC1 in the DC Characteristics table represents
A burst mode read operation is terminated using one of
three methods:
the active current specification for reading array data.
— In the first method, CE# is asserted high. The
device in this case remains in burst mode;
asserting LBA# low terminates the previous
burst read cycle and starts a new burst read
cycle with the address that is currently valid.
Requirements for Reading Array Data in
Synchronous (Burst) Mode
The device offers fast 32-word sequential burst reads
and is used to support microprocessors that implement
an instruction prefetch queue, as well as large data
transfers during system configuration.
— In the second method, the Burst Disable
command sequence is written to the device. The
device halts the burst operation and returns to
the asynchronous mode.
Three additional pins—Load Burst Address (LBA#),
Burst Address Advance (BAA#), and Clock (CLK)—
allow interfacing to microprocessors and microcontrol-
lers with minimal glue logic. Burst mode read is a syn-
chronous operation tied to the rising edge of CLK. CE#,
OE#, and WE# are asynchronous (relative to CLK).
— In the third method, RESET# is asserted low. All
operations are immediately terminated, and the
device reverts to the asynchronous mode.
Note that writing the reset command does not termi-
nate the burst mode.
When the device is in asynchronous mode (after
power-up or RESET# pulse), any signals on the CLK,
July 8, 2005
Am29BL162C
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SPANSION [ SPANSION ]
