D A T A S H E E T
PIN CONFIGURATION
A0–A19
=
20 addresses
BAA#
=
Burst Address Advance input.
Increments the address during the
burst mode operation
DQ0–DQ15 = 16 data inputs/outputs
CE#
OE#
WE#
=
=
=
Chip Enable Input. This signal shall be
asynchronous relative to CLK for the
burst mode.
BAA# Low enables the burst mode
Flash device to read from the next
word when gated with the rising edge
of the clock. Data becomes available
tBACC ns of burst access time after the
rising edge of the clock
Output Enable Input. This signal shall
be asynchronous relative to CLK for
the burst mode.
Write enable. This signal shall be
asynchronous relative to CLK for the
burst mode.
BAA # High prevents the rising edge of
the clock from advancing the data to
the next word output. The output data
remains unchanged.
VSS
NC
=
=
Device ground
IND#
=
=
Highest burst counter address
reached. IND# is low at the end of a
32-word burst sequence (when word
Da + 31 is output). The output wraps
around to Da on the next CLK cycle
(with BAA# low).
No connect. Pin not connected
internally
RY/BY#
CLK
=
=
Ready Busy output
Clock Input that can be tied to the
system or microprocessor clock and
provides the fundamental timing and
internal operating frequency. CLK
latches input addresses in conjunction
with LBA# input and increments the
burst address with the BAA# input.
RESET#
Hardware reset input
Note: The address, data, and control signals (RY/BY#, LBA,
BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant.
LOGIC SYMBOL
LBA#
=
Load Burst Address input. Indicates
that the valid address is present on the
address inputs.
20
A0–A19
16
LBA# Low at the rising edge of the
clock latches the address on the
address inputs into the burst mode
Flash device. Data becomes available
tPACC ns of initial access time after the
rising edge of the same clock that
latches the address.
DQ0–DQ15
CLK
CE#
OE#
IND#
WE#
RESET#
LBA#
LBA# High indicates that the address
is not valid
RY/BY#
BAA#
6
Am29BL162C
July 8, 2005
SPANSION [ SPANSION ]
