P r e l i m i n a r y I n f o r m a t i o n
AC Characteristics
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following AVD# falling edge
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is
set to “101”.
Figure 48. Example of Wait States Insertion
June 18, 2004 27024_A5_00_E
Am29BDS128H/Am29BDS064H
81
SPANSION [ SPANSION ]
