P r e l i m i n a r y
I n f o r m a t i o n
General Description
The Am29BDS128H/Am29BDS064H is a 128 or 64 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device, organized as 8,388,608 or
4,194,304 words of 16 bits each. This device uses a single V
CC
of 1.65 to 1.95 V
to read, program, and erase the memory array. A 12.0-volt V
HH
on ACC may be
used for faster program performance if desired. The device can also be pro-
grammed in standard EPROM programmers.
At 75 MHz, the device provides a burst access of 9.3 ns at 30 pF with a latency
of 49 ns at 30 pF. At 66 MHz, the device provides a burst access of 11 ns at 30
pF with a latency of 56 ns at 30 pF. At 54 MHz, the device provides a burst access
of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The device operates within
the industrial temperature range of -40°C to +85°C. The device is offered in
FBGA packages.
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into four banks. The device can improve overall
system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another bank, with zero latency.
This releases the system from waiting for the completion of program or erase op-
erations.
The device is divided as shown in the following table:
Quantity
Bank
A
B
C
D
128 Mb
8
31
96
96
31
8
64 Mb
8
15
48
48
15
8
Size
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
The VersatileIO™ (V
IO
) control allows the host system to set the voltage levels
that the device generates at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the V
IO
pin.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)
and Output Enable (OE#) to control asynchronous read and write operations. For
burst operations, the device additionally requires Ready (RDY), and Clock (CLK).
This implementation allows easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to
the device. The user can preset the burst length and wrap through the same
memory space, or read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock
edges, either rising or falling. The active clock edge initiates burst accesses and
determines when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-
power-supply Flash standard.
Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
June 18, 2004 27024_A5_00_E
Am29BDS128H/Am29BDS064H
3
SPANSION [ SPANSION ]
