A D V A N C E I N F O R M A T I O N
After the sector erase command is written, the system
DQ3: Sector Erase Timer
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the Sector Erase Command Sequence sec-
tion.
Table 15 shows the status of DQ3 relative to the other
status bits.
Table 15. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
1
No toggle
0
N/A
Toggle
Suspended Sector
Erase-Suspend-
Read (Note 4)
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
timing limits. Refer to the section on DQ5 for more
information.
1. DQ5 switches to ‘1’ when an Embedded Program or
Embedded Erase operation has exceeded the maximum
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchro-
nously (burst) while in erase suspend. RDY will function
exactly as in non-erase-suspended mode.
32
Am29BDS640G
May 9, 2002
SPANSION [ SPANSION ]
