P r e l i m i n a r y
Figure 32. Example of Wait States Insertion (Standard
Handshaking Device)........................................................ 68
Figure 33. Back-to-Back Read/Write Cycle Timings ............... 69
Erase/Program Operations ................................................................ 57
Figure 21. Asynchronous Program Operation Timings............. 58
Figure 22. Alternate Asynchronous Program Operation Timings 59
Figure 23. Synchronous Program Operation Timings.............. 60
Figure 24. Alternate Synchronous Program Operation Timings 61
Figure 25. Chip/Sector Erase Command Sequence................. 62
Figure 26. Accelerated Unlock Bypass Programming Timing.... 63
Figure 27. Data# Polling Timings (During Embedded Algorithm) 64
Figure 28. Toggle Bit Timings (During Embedded Algorithm)... 64
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings.
65
Erase and Programming Performance . . . . . . . . 70
FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 70
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 71
VBD064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm Package ..................................................................................71
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 30. Latency with Boundary Crossing .......................... 66
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank ................................................... 67
October 1, 2003 27243B1
Am29BDS320G
5
SPANSION [ SPANSION ]
