P r e l i m i n a r y
Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
Chip Erase Time
0.4
28
5
s
s
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Word Programming Time
11.5
4
210
120
75
µs
µs
s
Accelerated Word Programming Time
Chip Programming Time (Note 3)
Excludes system level
overhead (Note 5)
25
9
Accelerated Chip Programming Time
27
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 14 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
FBGA Ball Capacitance
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
4.2
5.4
3.9
Max
5.0
6.5
4.7
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
pF
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Data Retention
Parameter
Test Conditions
Min
10
Unit
150
°C
C
Years
Years
Minimum Pattern Data Retention Time
125
°
20
70
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
