P r e l i m i n a r y
AC Characteristics
7 cycles for initial access shown.
tCEZ
tCAS
CE#
1
2
3
4
5
6
7
8
CLK
tAVC
AVD#
tAVD
tAAS
tBDH
Aa
A20-A0
tBACC
tAAH
Hi-Z
DQ15-DQ0
Da
Da + 1
Da + n
tIACC
tACC
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed
from two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state
handshaking under a CLK synchronous burst mode.
October 1, 2003 27243B1
Am29BDS320G
53