P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS
tAS
AVD
tAH
tAVDP
Addresses
555h
PA
VA
VA
In
Data
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tAVSW
tWP
tWHWH1
tWPH
tWC
tCSW2
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A20–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
7. CLK must not have an active edge while WE# is at VIL
.
8. AVD# must toggle during command sequence unlock cycles.
Figure 23. Synchronous Program Operation Timings
60
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
