P r e l i m i n a r y
AC Characteristics
Erase/Program Operations
Parameter
All
Speed
Options
JEDEC
Standard
Description
Write Cycle Time (Note 1)
Unit
tAVAV
tWC
Min
Min
80
5
ns
Synchronous
Address Setup Time
(Note 2)
tAVWL
tAS
ns
ns
Asynchronous
Synchronous
Asynchronous
0
7
Address Hold Time
(Note 2)
tWLAX
tAH
Min
45
5
tACS
tACH
Address Setup Time to CLK (Note 2)
Address Hold Time to CLK (Note 2)
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
7
tDVWH
tWHDX
tGHWL
tDS
45
0
tDH
Data Hold Time
tGHWL
tCAS
Read Recovery Time Before Write
CE# Setup Time to AVD#
0
0
tWHEH
tWLWH
tWHWL
tCH
CE# Hold Time
0
tWP
Write Pulse Width
50
30
0
tWPH
tSR/W
tWHWH1
tWHWH1
Write Pulse Width High
Latency Between Read and Write Operations
Programming Operation (Note 3)
Accelerated Programming Operation (Note 3)
Sector Erase Operation (Notes 3, 4)
Chip Erase Operation (Notes 3, 4)
VACC Rise and Fall Time
tWHWH1
tWHWH1
8
2.5
0.4
28
500
1
tWHWH2
tWHWH2
Typ
sec
tVID
tVIDS
tVCS
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
VACC Setup Time (During Accelerated Programming)
VCC Setup Time
50
5
tCSW1
tCSW2
tCHW
tCS
Clock Setup Time to WE# (Asynchronous)
Clock Setup Time to WE# (Synchronous)
Clock Hold Time from WE#
CE# Setup Time to WE#
1
1
tELWL
0
tAVSW
tAVHW
tAVHC
tAVDP
AVD# Setup Time to WE#
5
AVD# Hold Time to WE#
5
AVD# Hold Time to CLK
5
AVD# Low Time
12
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are
latched on the first of either the rising edge of AVD# or the active edge of CLK.
3. See the “Erase and Programming Performance” section for more information.
4. Does not include the preprogramming time.
October 1, 2003 27243B1
Am29BDS320G
57
SPANSION [ SPANSION ]
