P r e l i m i n a r y
Input/Output Descriptions
A20-A0
DQ15-DQ0
CE#
=
=
=
Address inputs
Data input/output
Chip Enable input. Asynchronous relative to CLK for
the Burst mode.
OE#
=
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
VCC
=
=
Write Enable input.
Device Power Supply
(1.65 – 1.95 V).
VIO
=
Input & Output Buffer Power Supply (either 1.65 –
1.95 V or 2.7 – 3.15 V).
VSS
NC
RDY
=
=
=
Ground
No Connect; not connected internally
Ready output; indicates the status of the Burst read.
Low = data not valid at expected time. High = data
valid.
CLK
=
=
CLK is not required in asynchronous mode. In burst
mode, after the initial word is output, subsequent
active edges of CLK increment the internal address
counter.
Address Valid input. Indicates to device that the valid
address is present on the address inputs (A20–A0).
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
AVD#
High = device ignores address inputs
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At VIL, disables
program and erase functions in the two outermost
sectors. Should be at VIH for all other conditions.
At VID, accelerates programming; automatically
places device in unlock bypass mode. At VIL, locks all
sectors. Should be at VIH for all other conditions.
RESET#
WP#
=
=
ACC
=
Logic Symbol
21
A20–A0
16
DQ15–DQ0
CLK
WP#
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
10
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
