D a t a S h e e t
AC Characteristics
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode
Configuration Register, RDY is active one clock cycle before data.
4. AVD# must toggle between data reads.
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings
May 15, 2007 27243B2
Am29BDS320G
65
SPANSION [ SPANSION ]
