D A T A S H E E T
cause DQ6 to toggle. When the operation is complete,
RDY: Ready
DQ6 stops toggling.
The RDY is a dedicated output that, when the device is
configured in the Synchronous mode, indicates (when
at logic low) the system should wait 1 clock cycle before
expecting the next word of data. The RDY pin is only
controlled by CE#. Using the RDY Configuration
Command Sequence, RDY can be set so that a logic
low indicates the system should wait 2 clock cycles
before expecting valid data.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately t
time, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
, all sectors protected toggle
ASP
The following conditions cause the RDY output to be
low: during the initial access (in burst mode), and after
the boundary that occurs every 64 words beginning
with the 64th address, 3Fh.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7:
Data# Polling).
When the device is configured in Asynchronous Mode,
the RDY is an open-drain output pin which indicates
whether an Embedded Algorithm is in progress or com-
pleted. The RDY status is valid after the rising edge of
the final WE# pulse in the command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is in high imped-
ance (Ready), the device is in the read mode, the
standby mode, or in the erase-suspend-read mode.
Table 23, “Write Operation Status,” on page 52 shows
the outputs for RDY.
If a program address falls within a protected sector,
DQ6 toggles for approximately t
after the program
PSP
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
DQ6: Toggle Bit I
See the following for additional information: Figure 9,
“Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I”
on page 49, Figure 41, “Toggle Bit Timings
(During Embedded Algorithm),” on page 76 (toggle bit
timing diagram), and Table 22, “DQ6 and DQ2 Indica-
tions,” on page 51.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the
same bank, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Toggle Bit I on DQ6 requires either OE# or CE# to be
deasserted and reasserted to show the change in
state.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
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